The present invention relates to a semiconductor integrated circuit device, and more particularly to attainment of higher operation speed and lower power consumption in a semiconductor integrated circuit device.
In recent years, the market of multi-functional and low-power equipment has expanded, and semiconductor integrated circuit devices mounted in such equipment have been requested to attain higher operation speed and lower power consumption.
As a conventional semiconductor integrated circuit device that attains lower power consumption, a technology disclosed in Japanese Laid-Open Patent Publication No. 2004-165649 (Patent Literature 1), for example, is known. A semiconductor integrated circuit device described in Patent Literature 1 includes a substrate voltage adjustment circuit that adjusts the substrate voltage of a semiconductor substrate so that the drain current of a MOSFET for monitoring (element to be measured for monitoring) and the drain current of a plurality of MOSFETs in an integrated circuit body are constant. In this semiconductor integrated circuit device, the substrate voltage of MOSFETs is controlled to prevent a drain current at a gate voltage value in a subthreshold range or saturation range of the MOSFETs from having dependencies on the temperature and process variations.
FIG. 11 is a block diagram of the entire structure of a semiconductor integrated circuit device adopting the substrate voltage adjustment technology disclosed in Patent Literature 1.
Referring to FIG. 11, a semiconductor integrated circuit device 10 includes: an integrated circuit body 16 having a plurality of MOSFETs on a semiconductor substrate; a drain current monitor circuit 15 for monitoring the drain current of a MOSFET 11 for monitoring; and a substrate voltage adjustment circuit 14 for adjusting the substrate voltage Vb of the semiconductor substrate so that the drain current of the MOSFET 11 for monitoring is constant.
The drain current monitor circuit 15 includes a constant current source 12. The MOSFET 11 for monitoring is formed on the same substrate as the plurality of MOSFETs in the integrated circuit body 16, and the gate of the MOSFET 11 for monitoring is set at a given voltage 17 equal to or less than the power supply voltage VDD for the integrated circuit body 16.
The substrate voltage adjustment circuit 14 includes a comparator circuit 13 that compares the source potential of the MOSFET 11 for monitoring with a preset reference potential in the state of the drain terminal of the MOSFET 11 for monitoring and the drain terminals of the plurality of MOSFETs in the integrated circuit body 16 being connected to the ground potential VSS. The comparison result from the comparator circuit 13 is fed back to the substrate voltage Vb of the MOSFET 11 for monitoring to thereby adjust the substrate voltage Vb.
As a semiconductor integrated circuit device that attains both higher operation speed and lower power consumption, there is a technology disclosed in Japanese Laid-Open Patent Publication No. 2001-345693 (Patent Literature 2), for example, in which characteristic variations of semiconductor integrated circuit devices are suppressed to improve the circuit performance.
FIG. 12 is a block diagram of the entire configuration of a semiconductor integrated circuit device disclosed in Patent Literature 2.
A semiconductor integrated circuit device 20 of FIG. 12 monitors a chain of serially-connected inverter circuits as an element to be measured for monitoring (not shown) with a monitor circuit (not shown), and controls the operation frequency, the power supply voltage and the substrate voltage based on a measured parameter of the element to be measured for monitoring.
In the semiconductor integrated circuit device 20, the measured parameter of the element to be measured for monitoring is supplied to a command issuance circuit 21. Thereafter, based on command signals CS1, CS2 and CS3 from the command issuance circuit 21, a clock frequency control circuit 22, a power supply voltage control circuit 23 and a substrate voltage control circuit 24 respectively control the clock signal, the power supply voltage and the substrate voltage, and then supply the resultant clock signal, power supply voltage and substrate voltage to an integrated circuit body 25 that includes register circuits REG01 and REG02 and a logic circuit LOG. With this semiconductor integrated circuit device 20, the power consumption can be reduced without lowering the operation speed, or the operation speed can be improved without increasing the power consumption.
However, the semiconductor integrated circuit devices of Patent Literature 1 and Patent Literature 2 described above have the following problems. If the element to be measured for monitoring itself has fabrication variations in which variations occur locally and randomly during fabrication (hereinafter, called “local variations”), such local variations may affect the adjustment of an operation parameter such as the substrate voltage.
The local variations increase in submicron processes due to fluctuations caused by randomness of a discrete impurity distribution and characteristic fluctuations caused by line edge roughness of gate polysilicon. For this reason, in the case that the element to be measured for monitoring is a MOSFET in Patent Literature 1 and Patent Literature 2 described above, it is unknown whether the measured parameter that is the drain current of the MOSFET for monitoring is the maximum, the minimum or the median in the local variation distribution. If the substrate voltage control is performed at the time when the drain current of the MOSFET for monitoring is characterized as the maximum in the local variation distribution, the integrated circuit body may possibly fail to operate.
Also, in the case that the element to be measured for monitoring is a delay circuit composed of serially connected inverter circuits, the integrated circuit body may possibly fail to operate if a delay circuit that is minimum in delay time in the local variation distribution is monitored as the element to be measured for monitoring.